The present invention relates to methods and apparatus for computation circuits, power and energy measuring circuits, and more particularly to analog computation circuits, power meters, and energy meters that use a synchronous demodulation topology.
Computation circuits may determine a product or ratio of two or more analog signals while maintaining proper units. Traditional computational circuits such as multiplier/divider circuits, may use a variety of methods to perform circuit computations. Such methods may use the logarithmic characteristic of the current versus voltage (I-V) curve of the bipolar transistor Vbe-Ic or the square-law characteristic of the MOSFET Vgs-Id relationships to implement multiplier/divider circuits. Both methods may have inherent accuracy limitations in performing computations because of their dependence upon Vbe/Vgs control voltages. These control voltages are often relatively low voltages that can be subjected to variations (e.g., thermal changes, transients, noise, or the like) which may hinder the computation circuit""s computational accuracy.
Some multiplier/divider circuits have departed from the traditional computational circuit methods, such as the multiplier/divider circuit described in U.S. Pat. No. 5,150,324 to Takasuka et al., the disclosure of which is incorporated by reference in its entirety (hereinafter xe2x80x9cTakasukaxe2x80x9d). FIG. 1 illustrates a simplified version of Takasuka""s FIG. 1. Takasuka circuit 100, as shown in FIG. 1, may be configured to perform multiplication, division, or other computations. This circuit may use a delta-sigma modulator 130, which has analog inputs V1 and VREF. Modulator 130 may generate a digital output signal (e.g., duty cycle) based on a ratio having V1 inversely proportional to VREF. This digital output signal (ratio) can be used as an input for multiplying digital-to-analog converter 151 (MDAC 151). MDAC 151 may also receive a second input signal, which is shown as V2. MDAC 151 may generate a signal by multiplying the digital output signal with the second input signal at V2. The result may be filtered by lowpass filter 160 to produce output VOUT, which may be substantially equivalent to (V1/VREF)*V2.
This circuit has significant improvements over the traditional methods, but still has several flaws. One flaw with Takasuka circuit 100 may be that the sampling frequency should be several times higher (e.g., 50-1000 times) than the input frequency of V1. When the frequency of V1 approaches the sampling frequency of clock CLK, modulator 130 may experience amplitude roll-off of the input signal V1. This may result in errors that occur during multiplication of the digital signal and V2 in MDAC 151 because of delays in modulator 130. Since both modulator 130 and MDAC 151 operate at the same clock frequency, any delay in generating the digital signal may result in an erroneous measurement. Takasuka circuit 100 may have another restriction that requires the frequency of VREF to be much lower than the sampling frequency in order to keep modulator 130 stable.
FIG. 2 shows RMS-to-DC converter 200 as described in U.S. Pat. No. 5,896,056 to Glucina, the disclosure of which is incorporated by reference in its entirety. RMS-to-DC converter 200 may include xcex94-xcexa3 modulator 230, MDAC 250, lowpass filter 260, rectifier 205 to provide computation of the RMS function. Rectifier 205 may be coupled to receive V1 and V2 and provide an output to both xcex94-xcexa3 modulator 230 and MDAC 250. xcex94-xcexa3 modulator 230 may generate a digital signal based on the rectifier output and the output of lowpass filter 260, shown as VOUT. The output of lowpass filter 260, VOUT may provide a unipolar DC signal that provides xcex94-xcexa3 modulator 230 with a stable reference, VREF for generating a digital output signal. This digital output signal may then be multiplied to the rectified signal produced by rectifier 205 to create an analog signal that can be filtered by lowpass filter 260.
The filtered analog product can be accurate, but often times the result is hampered by delays introduced by xcex94-xcexa3 modulator 230. Delays introduced by xcex94-xcexa3 modulator 230 can degrade the overall accuracy of RMS-to-DC converter 200 because multiplication of the digital output signal and the rectifier output are not synchronous. That is, the multiplication of the digital output signal and the rectifier output in DAC 250 is not based on the same sample time. Furthermore, rectifier 205 may introduce delay errors during rectification of small signals operating at relatively high frequency because of switching transients and voltage drops across the diodes, transistors, etc.
FIG. 3 shows another illustrative embodiment of a RMS-to-DC converter 300 as described in commonly assigned, co-pending, U.S. patent application Ser. No. 09/411,150, filed Oct. 1, 1999, the disclosure of which is incorporated by reference in its entirety. Converter 300 may have Synchronous MASH Modulator/Demodulator (SMMD) circuitry (i.e., pulse code modulator 330, demodulator 350, and delay stages 322 and 324) for performing RMS-to-DC conversion of input signals that have a bipolar input signal range, thus eliminating the need for a performance degrading rectifier. MASH is constituted by a cascade of at least two first order xcex94-xcexa3 modulators. Modulator 330 includes cascaded single-sample xcex94-xcexa3 stages 332 and 334 and demodulator 350 includes single-bit multiplying digital-to-analog converters (MDAC) stages 352, 354, and 356, and adder/subtractor 358.
SMMD circuitry assures that the multiplication that happens at each MDAC is synchronous; that is both the digital signal generated by the modulator and the delayed analog signal are from the same input sample of VIN. The MDACs need not be synchronous with each other, but each one should multiply a digital input with an analog input that is substantially from the same input sample. The products generated by DAC stages 352, 354, and 356 may be summed in adder/subtractor 358. The output of adder/subtracter, shown as MDOUT, may be filtered by low pass filter 360 and amplified by gain stage 372 to provide VOUT. VOUT may be fed back to gain stage 374 which provides a reference signal for xcex94-xcexa3 stages 332 and 334.
Converter 300 may not be limited to having input signals with frequencies less than the sampling frequency of the modulator. In fact, the input frequency may equal or exceed the sampling frequency of the RMS-to-DC converter. This may be possible because the RMS value of an alias of a signal is the same as the RMS value of the signal itself and also because SMMD topology does not corrupt the amplitude vs. frequency response as do all known prior art RMS-to-DC converters using pulse code modulators. The behavior with low over-sampling ratios and even under-sampled waveforms may be further enhanced by the technique of clock dithering as described in commonly assigned, co-pending patent application Ser. No. 09/735,331, filed Dec. 12, 2000, the disclosure of which is incorporated by reference in its entirety.
Power measuring circuits have traditionally been configured with electro-mechanical devices that obtain current by measuring the magnetic field. These meters, however, are expensive and not very cost-effective for use in tiered energy pricing applications or for remote data collection stations.
Other power measuring circuits have been configured to use digital circuits to obtain power and energy measurements. Digital circuits such as the AD7750 manufactured by Analog Devices of Norwood, Massachusetts, and the CS5460 manufactured by Cirrus Logic of Fremont, Calif., have both been used to measure power and energy. These circuits use digitized signals to represent load voltage and current when performing power and energy computations in the digital domain. However, performing such digital calculations can be impractical because a substantial quantity of power is dissipated when obtaining the power or energy measurement.
Another device that can be used for measuring power is described in EDN Magazine, published on Dec. 23, 1999 which discloses the use of U.S. Pat. No. 5,867,054 to Kotowski, both disclosures of which are incorporated by reference in their entirety. Kotowski""s circuit may use a pulse-code modulation technique to measure the average power consumed by a load. However, the power measuring circuit disclosed by the EDN article may have limited utility for AC power measurement. This may be because Kotowski""s circuit only operates over a portion of the AC power signal. Furthermore, the current signal is delayed considerably by the internal digital filter, which may result in significant power measurement error.
In view of the foregoing, it would be desirable to provide an analog computation circuit that utilizes a synchronous demodulation topology.
It would also be desirable to provide an analog circuit that measures power using a synchronous demodulation topology.
It would be further desirable to provide an analog circuit that measures energy using a synchronous demodulation topology.
It is therefor an object of this invention to provide an analog computation circuit that utilizes a synchronous demodulation topology.
It is also an object of this invention to provide an analog circuit that measures power by utilizing synchronous demodulation.
It is a further object of this invention to provide an analog circuit that measures energy by utilizing a synchronous demodulation topology.
In accordance with these and other objects of the present invention, analog computation circuits using a synchronous demodulator topology may be configured to perform arithmetic computation, power measurements, and/or energy measurement of various analog signals. The computation circuits, of the present invention, may have circuitry such as modulation circuitry (e.g., xcex94-xcexa3 modulation circuitry), demodulation circuitry (e.g., multiplying digital-to-analog converters), delay circuitry, and output circuitry that generates an output signal based on two analog signals and a reference signal.
Analog computation circuits such as computation circuits, power measuring circuits, energy measuring circuits, or any other suitable type of circuit may accurately compute the product of two analog signals based upon the same sample clock signal when these two signals are synchronously multiplied together in the demodulation circuitry. The modulation circuitry may generate a digital output signal of a first analog signal that is inversely proportional to a reference signal.
The generation of this digital output signal may not be an instantaneous process, in fact, there may be delay associated with the generation of the digital output signal. In order to ensure that a second analog signal is synchronously multiplied with the first analog signal, which has been converted to the digital output signal, the second input signal may be delayed to compensate for the delay occurring in the generation of the digital output signal. The demodulation circuitry multiplies the delayed second signal and digital output signal to produce an output signal. Output circuitry may filter the product signal of the demodulation circuitry. The filtered output signal may be proportional to the first and second analog signals and inversely proportional to the reference signal.